In conventional monolithic driver-type display devices, apart from a video signal line driver circuit (hereinafter, referred to as a “source driver”) and a scanning signal line driver circuit (hereinafter, referred to as a “gate driver”), logic circuits, such as D-type flip-flop circuits for converting serial-format digital video signals (hereinafter, the “digital video signal” being referred to as the “video signal”) into parallel-format video signals, are formed in a silicon layer made of, for example, continuous grain silicon (hereinafter, referred to as “CG silicon”) deposited on an insulating substrate. In this case, in order for the logic circuits to convert video signals, which are low-voltage swing signals in serial format, into parallel format, it is necessary to increase the swing of the inputted video signals to the level of the power-supply voltage of the logic circuits. However, when the source driver is driven using the video signals having a high voltage swing increased by the logic circuits for serial-parallel conversion, parasitic capacitances on data lines formed on the insulating substrate increase, resulting in increased power consumption of the display device.
Accordingly, in Japanese Laid-Open Patent Publication No. 2006-173812, video signals having their voltage swing increased by level adjustment circuits are subjected to serial-parallel conversion by logic circuits, and thereafter the voltage swing of the video signals is reduced by level-down converters for output to the source driver. Therefore, it is not necessary to use video signals with an increased voltage swing to drive the source driver through data lines with increased parasitic capacitances, so that power consumption of the display device can be kept low.
Also, in Japanese Laid-Open Patent Publication No. 9-244583, an analog video signal is expanded into three phases by three sampling switches, and then held in capacitors, and analog video signals with their black levels fixed by clampers are supplied to the display portion.    [Patent Document 1] Japanese Laid-Open Patent Publication No. 2006-173812    [Patent Document 2] Japanese Laid-Open Patent Publication No. 9-244583